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rev description date prep appd c co - 15263 7 /1 5 /0 9 sm hw date vectron international mount holly springs, pa 17065 prepared by s. murphy 6/19/08 specification, hybrid tcxo quality r. smith 6/19/08 hi-rel standard engineering h. wilson 6/19/08 code ident no size dwg. no. rev 00136 a DOC200103 c unspecified tolerances: n/a sheet 1 0f 20
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 2 1. scope 1.1 general. this specification defines the design, as sembly and functional evaluation of high reliability, hybrid tcxos produced by vectron inter national. devices delivered to this specification represent the standardized parts, mat erials and processes (pmp) program developed, implemented and certified for advanced a pplications and extended environments. 1.2 applications overview. the designs represented by these products were primarily developed for the mil-aerospace community. the lesser design pedigrees and screening options imbedded within DOC200103 bridge the gap between sp ace and cots hardware by providing custom hardware with measures of mechanical, assemb ly and reliability assurance needed for military, ruggedized cots or commercial environment s. 2. applicable documents 2.1 specifications and standards. the following specif ications and standards form a part of this document to the extent specified herein. the issue currently in effect on the date of quotation will be the product baseline, unless otherwise spec ified. in the event of conflict between the texts of any references cited herein, the text of t his document shall take precedence. military mil-prf-55310 oscillators, crystal controlled, gene ral specification for mil-prf-38534 hybrid microcircuits, general specifi cation for standards mil-std-202 test method standard, electronic and el ectrical component parts mil-std-883 test methods and procedures for microel ectronics mil-std-1686 electrostatic discharge control progra m for protection of electrical and electronic parts, assemblies and equipment vectron international ht-67849 test specification, os-68338 hybrids, hi-r el standard qsp-90100 quality systems manual, vectron internati onal vl-65339 identification common documents, materials and processes, hi-rel xo 3. general requirements 3.1 classification. all devices delivered to this specification are of hybrid technology conforming to type 1, class 2 of mil-prf-55310. primarily dev eloped as a class s specification, options are imbedded within it to also produce class b, eng ineering model and commercial model devices. devices carry a class 2 esds classificati on.
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 3 3.2 item identification. external packaging choice s are either metal flatpacks or ddip with either sinewave or cmos logic output. unique model number series? are utilized to identify device package configurations and output waveform as liste d in table 1. 3.3 absolute maximum ratings. a. supply voltage range (v cc ): -0.5vdc to +7.0vdc (cmos) b. storage temperature range (t stg ): -65c to +125c c. junction temperature (t j ): +175c d. lead temperature (soldering, 10 seconds): +300c e. output source/sink current 50 ma 3.4 design, parts, materials and processes, assembl y, inspection and test. 3.4.1 design. the ruggedized designs implemented f or these devices are proven in military and space applications under extreme environments. all designs utilize a 4-point crystal mount. when class s is specified, a radiation tolerance of 100krad (si) (rha level r) is included without altering the device?s internal topography. for all class s and class b products, components meet the element evaluation requirements of mil-prf-55310, appendix b. if design pedigree code ?e? is chosen, enhanced elemen t evaluation per appendix a will be performed. 3.4.1.1 design and configuration stability. barrin g changes to improve performance by reselecting passive chip component values to offset component t olerances, there will not be fundamental changes to the design or assembly or parts, materia ls and processes after first product delivery of that item without written approval from the proc uring activity. 3.4.1.2 environmental integrity. designs have pass ed the environmental qualification levels of mil- prf-55310. these designs have also passed extended dynamic levels of at least: sine vibration: mil-std-202, method 204, condition g (30g pk.) random vibration: mil-std-202, method 214, conditio n ii-j (43.92g rms) mechanical shock: mil-std-202, method 213, conditio n f (1500g, 0.5ms) 3.4.2 prohibited parts, materials and processes. t he items listed are prohibited for use in high reliability devices produced to this specification. a. gold metallization of package elements without a barrier metal. b. zinc chromate as a finish. c. cadmium, zinc, or pure tin external or internal to the device. d. plastic encapsulated semiconductor devices. e. ultrasonically cleaned electronic parts. f. heterojunction bipolar transistor (hbt) technolo gy. 3.4.3 assembly. manufacturing utilizes standardize d procedures, processes and verification methods to produce mil-prf-55310 class s / mil-prf- 38534 class k equivalent devices. mil-prf-38534 group b option 1 in-line inspection i s included on radiation hardened part numbers to further verify lot pedigree. traceabili ty of all components and production lots are
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 4 in accordance with mil-prf-38534, as a minimum. ta bulated records are provided as a part of the deliverable data package. devices are handl ed in accordance with mil-std-1686 for class 1 devices. 3.4.4 inspection. the inspection requirements of m il-prf-55310 apply to all devices delivered to this document. inspection conditions and standards are documented in accordance with the quality assurance, iso-9001 derived, system of qsp- 90100. 3.4.5 test. the screening test matrix of table 4 i s tailored for selectable-combination testing to eliminate costs associated with the development/mai ntenance of device-specific documentation packages while maintaining performance integrity. 3.4.6 marking. device marking shall be in accordan ce with the requirements of mil-prf-55310. 3.4.7 ruggedized cots design implementation. desig n pedigree ?d? devices (see ? 5.2) use the same robust designs found in the other device pedig rees. they do not include the provisions of traceability or the class-qualified componentry not ed in paragraphs 3.4.3 and 4.1. 4. detail requirements 4.1 components 4.1.1 crystals. cultured quartz crystal resonators are used to provide the selected frequency for the devices. premium q swept quartz is standard for al l class s level products because of its superior radiation tolerance. for class b level pr oducts, swept quartz is optional, as required by the customer. in accordance with mil-prf-55310, the manufacturer has a documented crystal element evaluation program. 4.1.2 passive components. where possible, establis hed reliability (er) failure level r and s passive components are employed. otherwise, all co mponents comply with the element evaluation requirements of mil-prf-55310, appendix b. 4.1.3 class s microcircuits. microcircuits are pro cured from wafer lots that have passed mil-prf- 55310 lot acceptance tests for class s devices. th e prescribed die carries a class 2 esds classification in accordance with mil-prf-38535. a lthough radiation testing is not performed at the oscillator level, design pedigree codes e an d r versions of this tcxo are acceptable for use in environments of up to 100 krads total do se by analysis of the individual components. sinewave devices are assembled with all bipolar sem iconductors. acmos devices are assembled with all bipolar semiconductors with the exception of the acmos chip used to provide the cmos output. an acmos die from a radia tion tested and certified wafer lot will be provided for all class s versions of this tcxo. this microcircuit is certified for 100krad(si) total ionizing dose (tid), rha level r (2x minimum margin). nsc, as the 54act designer, rates the seu let at >40 mev and se l at >120mev for the fact? family (an-932). our wafer testing does not includ e these parameters and determinations, but
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 5 by design similarity. a copy of the parts list and materials can be provided for customer review upon request. 4.1.3.1 class b microcircuits. when specified, mic rocircuits assembled into pedigree codes b and c devices (? 5.2a) are procured from wafer lots that have passed mil-prf-55310 element evaluations for class b devices. 4.1.4 packages. packages are procured that meet th e construction, lead materials and finishes as specified in mil-prf-55310. package lots are upscr eened in accordance with the requirements of mil-prf-38534 as applicable. 4.1.5 traceability. class s active device lots are homogenous and traceable to the manufacturer?s individual wafer. swept quartz crystals are tracea ble to the quartz bar and the processing details of the autoclave lot, as applicable. all o ther elements and materials are traceable to their incoming inspection lots. manufacturing lot and date code information shall be recorded, by tcxo serial number, of every component and all m aterials used in the manufacture of that tcxo. all semiconductors used in the manufacture o f a given production lot of tcxos shall be from the same wafer and have the same manufactur ing lot date code. a production lot, as defined by vectron, is all oscillators that have be en kitted and assembled as a single group. after the initial kitting and assembly, this produc tion lot may be divided into multiple sublots to facilitate alignment and test capacity and may b e sealed at multiple times within a 13 week window. 4.2 mechanical. 4.2.1 package outline. table 1 links each hi-rel standard model number of this specification to a corresponding package style. mechanical outline in formation of each package style is found in the referenced figure. 4.2.2 thermal characteristics. because these tcxos are multichip hybrid designs, the actual jc to any one given semiconductor die will vary, but the combined average for all active devices results in a jc of approximately 40c/w. the typical die temperatu re rise at any one given semiconductor is 2c to 4c. with the oscillator o perating at +125c, the average junction temperature is approximately +129c and under no ci rcumstance will it ever exceed the maximum manufacturer?s rated junction temperature o f +150c. 4.3 electrical. 4.3.1 input power. cmos devices are designed for 3 .3 or 5.0 volt dc operation, 5%. sinewave devices are designed for 5.0, 12.0 or 15.0 volt dc operation, 5%. 4.3.2 temperature range. operating range is iaw th e chosen temperature stability code. 4.3.3 frequency tolerance. temperature stability i ncludes initial accuracy at +25c (with efc), load 10% and supply 5%. all devices include an e fc pin and the external frequency
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 6 adjustment shall be accomplished by connecting a re sistor or trimmer potentiometer from it to gnd. the resistance range is 0 or gnd to 20k max. nominal frequency typically occurs in the range of 7.5k to 12.5k . 4.3.4 frequency aging. aging limits, when tested i n accordance with mil-prf-55310 group b inspection, shall not exceed 1 ppm for the first y ear and 5 ppm for 10 years for oscillators that use crystals in the 10 mhz to 75 mhz range. f or oscillators that use crystals greater than 75 mhz, the aging shall not exceed 2 ppm for the f irst year and 10 ppm for 10 years. 4.3.4.1 frequency aging duration option. by custom er request, the aging test may be terminated after 15 days if the measured aging rate is less th an half of the specified aging rate. this is a common method of expediting 30-day aging without in curring risk to the hardware and used quite successfully for numerous customers. it is b ased on the ?least squares fit? determinations of mil-prf-55310 paragraph 4.8.35. the ?half the t ime/half the spec? limit is generally conservative as roughly 2/3 of a unit?s aging devia tion occurs within that period of time. vectron?s automated aging systems acquire data ever y four hours, compared to the minimum mil-prf-55310 requirement of once every 72 hours. this makes an extensive amount of data available to perform very accurate aging projection s. the delivered data would include the aging plots projected to 30 days. if the units wou ld not perform within that limit then they would continue to the full 30 day term. please adv ise by purchase order text if this may be an acceptable option to exercise as it assists in prod uction test planning. 4.3.5 operating characteristics. see tables 2 and 3. waveform measurement points and logic limits are in accordance with mil-prf-55310. start -up time is 10 msec typical and 30 msec maximum. 4.3.6 output load. standard sinewave (50 ohms) and cmos (10k , 15pf) test loads are in accordance with mil-prf-55310. 4.3.7 phase noise. contact factory for typical per formance. if custom and/or guaranteed performance is required, vectron can assign a custo m part number. 5. quality assurance provisions and verification 5.1 verification and test. device lots shall be tested prior to delivery in accordance with the applicable screening option letter as stated by the 16 th character of the part number. table 5 tests are conducted in the order shown and annotate d on the appropriate process travelers and data sheets of the governing test procedure. for d evices that require screening options that include mil-prf-55310 group a testing, the post-bur n-in electrical test and the group a electrical test are combined into one operation. 5.1.1 screening options. the screening options, by lette r, are summarized as: (s) mil-prf-55310 class s screening, groups a & b qci (c) modified mil-prf-55310 class b screening, groups a & b qci (b) mil-prf-55310 class b screening, groups a & b qci
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 7 (x) engineering model (em) (z) commercial model (cm) 5.2 optional design, test and data parameters. the following is a list of design, assembly, inspection and test options that can be selected or added by purchase order request. a. design pedigree (choose one as the 5 th character in the part number): (e) class s components, enhanced element evaluation, sw ept quartz (r) class s components, swept quartz (b) class b components, swept quartz (c) class b components, cultured quartz (d) cots components, cultured quartz b. input voltage as the 15 th character c. frequency-temperature slew test d. radiographic inspection e. group c inspection: mil-prf-55310 (requires 8 pc . sample) f. group c inspection: mil-prf-38534 (requires 8 pc . sample ? 5 pc. life, 3 pc. rga) g. internal water-vapor content (rga) samples and t est performance h. mtbf reliability calculations i. worst case/derating analysis j. deliverable process identification documentation (pid) k. customer source inspection (pre-cap / final) 5.3 test conditions. unless otherwise stated herein, i nspections are performed in accordance with those specified in mil-prf-55310. process traveler s identify the applicable methods, conditions and procedures to be used. examples of electrical test procedures that correspond to mil-prf-55310 requirements are shown in table 3. 5.4 deliverable data. the manufacturer supplies the fo llowing data, as a minimum, with each lot of devices: a. completed assembly and screening lot travelers, including rework history. b. electrical test variables data, identified by un ique serial number. c. frequency-temperature slew plots, radiographic d ata, group c data and rga data as required by purchase order. 5.5 discrepant material. all mrb authority resides wit h the procuring activity. 5.6 failure analysis. any catastrophic failure (no out put, no input current) at post burn-in or after will be evaluated for root cause. the customer wil l be notified after occurrence and upon completion of the evaluation. 6. preparation for delivery 6.1 packaging. devices will be packaged in a manner th at prevents handling and transit damage during shipping. devices will be handled in accord ance with mil-std-1686 for class 1 devices.
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 8 7. ordering information 7.1 ordering part number. the ordering part number is made up of an alphanumeric series of 16 characters. design-affected product options, identified by the parenthetic letter on the optional parameters list (? 5.2a and b), are in cluded within the device part number. the part number breakdown is described as: 2101 r 100m0000 e b s 7.1.1 model number. the device model number is the four (4) digit number assigned to a corresponding package and output combination per ta ble 1. 7.1.2 design pedigree. class s designs correspond to let ters ?e? and ?r? and are described in paragraph 5.2a. class b variants correspond to eit her letter ?b? or ?c? and are described in paragraph 5.2a. ruggedized cots, using commercial grade components, correspond to letter ?d?. 7.1.2.1 input voltage. voltage is the 15 th character. voltage availability is dependant on p latform. 7.1.3 output frequency. the nominal output frequency is expressed in the format as specified in mil-prf-55310 utilizing eight (8) characters. 7.1.4 screening options. the 16 th character is the screening option selected from ta ble 4. model # (table 1) input voltage a = +3.3v b = +5v c = +12v d = +15v design pedigree e = class s components, enhanced element evaluation swept quartz r = class s components, swept quartz b = class b components, swept quartz c = class b components, cultured quartz d = ruggedized cots: cultured quartz, commercial grade components temperature stability a = 0.5ppm, 0c to +50c b = 1ppm, 0c to +50c d = 1ppm, 0c to +70c f = 2ppm, 0c to +70c i = 5ppm, 0c to +70c k = 1ppm, -20c to +70c m = 2ppm, -20c to +70c r = 5ppm, -20c to +70c v = 4ppm, -40c to +85c w = 5ppm, -40c to +85c y = 10ppm, -55c to +105c screening option per table 4, 5.1.1
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 9 7.2 optional design, test and data parameters. tes t and documentation requirements above that of the standard high reliability model shall be spe cified by separate purchase order line items (as listed in ? 5.2c thru k). 1 /. all unassigned pins have no internal connection s or ties. table 1 - item identification and package outline pin i/o 1 / hi-rel standard model # package output vcc out gnd/case efc mechanic al outline 2101 24 pin ddip cmos 24 13 12 1 figure 1 2102 32 lead flatpack cmos 11, 13 12 5 4 figure 2 2103 24 lead flatpack cmos 24 13 12 1 figure 3 2104 14 lead flatpack cmos 2 13 1, 3, 7, 12, 14 6 figure 4 2111 24 pin ddip sine 24 13 12 1 figure 1 2112 32 lead flatpack sine 11, 13 12 5 4 figure 2 2113 24 lead flatpack sine 24 13 12 1 figure 3 2114 14 lead flatpack sine 2 13 7, 14 6 figure 4
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 10 1 /. waveform measurement points and logic limits ar e in accordance with mil-prf-55310. 2/. tested with 2 cmos loads. table 2 - electrical performance characteristics table 2a - electrical performance characteristics table 2b - electrical performance characteristics table 2c - electrical performance characteristics models 2101, 2102, 2103, 2104 supply voltage options1 /: +3.3v or +5v frequency range (mhz) current (ma) (max, no load) 5.25v | 3.465v rise / fall times (ns max.)2 / duty cycle (%) max cmos loads 5.25v | 3.465v 0.300 - 100 50 35 5 40 to 60 10 5 model 2111 supply voltage options: +5v, +12v or +15v frequency range (mhz) current (ma) (max, no load) 5v |12v/15v min power out (dbm) 5v | 12v/15v harmonics/ subharmonics (>75mhz) (dbc) spurious (dbc) 10 - 225 20 35 +3 +7 <-20 <-70 models 2112, 2114 supply voltage options: +5v, +12v or +15v frequency range (mhz) current (ma) (max, no load) 5v |12v/15v min power out (dbm) 5v |12v/15v harmonics/ subharmonics (>75mhz) (dbc) spurious (dbc) 10 - 150 20 35 +3 +7 <-20 <-70 model 2113 supply voltage options: +12v or +15v frequency range (mhz) current (ma) (max, no load) 12v | 15v min power out (dbm) 12v | 15v harmonics/ subharmonics (>75mhz) (dbc) spurious (dbc) 10 - 425 25 35 +5 +7 <-20 <-70
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 11 operation listing requirements and conditions vectron test procedure @ all electrical tests input current (no load) mil-prf-55310, para 4.8.5.1 gr-51681 initial accuracy @ ref. temp. mil-prf-55310, para 4 .8.6 gr-51596 output logic voltage levels mil-prf-55310, para 4.8 .21.3 gr-51597 rise and fall times mil-prf-55310, para 4.8.22 gr-5 1599 duty cycle mil-prf-55310, para 4.8.23 gr-51601 @ post burn-in electrical only overvoltage survivability mil-prf-55310, para 4.8.4 gr-37269 initial freq. ? temp. accuracy mil-prf-55310, para 4.8.10.1 gr-51602 freq. ? voltage tolerance mil-prf-55310, para 4.8.1 4 gr-51602 start-up time (fast/slow start) mil-prf-55310, para 4.8.29 gr-61352 table 3 - electrical test parameters
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 12 screening & testing options option code s c b x z screening (by class similarity) mil-prf-55310 class ?s? mil-prf-55310 class ?b? modified mil-prf-55310 class ?b? engineering model (em) commercial model (cm) non-destruct wire bond pull 100% n/a n/a n/a n/a internal visual m883, method 2017 for class ?s? m883, method 2017 for class ?b? m883, method 2017 for class ?b? m883, method 2017 for class ?b? aql sample stabilization bake 48 hrs min @ +150 c 48 hrs min @ +150 c 48 hrs min @ +150 c 24 hrs min @ +150 c 24 hrs min @ +150 c thermal shock m883, method 1011, tc ?a? n/a n/a n/a n/a temperature cycling m883, method 1010, tc ?b? m883, method 1010, tc ?b? m883, method 1010, tc ?b? n/a n/a constant acceleration m883, method 2001, tc ?a? (5000 g, y1 axis only) m883, method 2001, tc ?a? (5000 g, y1 axis only) m883, method 2001, tc ?a? (5000 g, y1 axis only) n/a n/a seal test (fine & gross) 100% 100% 100% 100% aql sample pind m883, method 2020, tc ?b? m883, method 2020, tc ?b? n/a n/a n/a electrical test frequency, output levels, input current @ +25 c only @ +25 c only @ +25 c only @ +25 c only @ +25 c only burn-in (powered with load) +125 c for 240 hours +125 c for 160 hours +125 c for 160 hours n/a n/a electrical test frequency, output levels, input current @ +25 c & temp extremes @ +25 c & temp extremes @ +25 c & temp extremes n/a n/a pda 2% applies to input current @ +25 c 10% applies to input current @ +25 c 10% applies to input current @ +25 c n/a n/a radiographic m883, method 2012 n/a n/a n/a n/a group ?a? inspection 100% sample per mil-prf-55310 sample per mil-prf-55310 n/a n/a group ?b? inspection (30 day aging @ +70 c) 100% sample per mil-prf-55310 sample per mil-prf-55310 n/a n/a table 4 - screening & test matrix
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 13 figure 1 models 2101 & 2111 package outline replaces vectron legacy models 566, 567, 929 and 93 0
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 14 figure 2 models 2102 & 2112 package outline replaces vectron legacy models 623 and 1623
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 15 figure 3 models 2103 & 2113 package outline replaces vectron legacy model 568
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 16 figure 4 models 2104 & 2114 package outline replaces vectron legacy model 2501
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 17 appendix a enhanced element evaluation (sheets 18 through 20)
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 18 microcircuit enhanced element evaluation subgroup class test mil-std-883 quantity mil-prf- 38534 reference k method condition (accept number) paragraph 1 x element electrical a. may perform at wafer level b. all failures shall be removed from the lot c. perform at room ambient 100% c.3.3.1 2 x element visual 2010 100% c.3.3.2 3 x internal visual 2010 10(0) or 22(0) (see notes 1 & 2) c.3.3.3 c.3.3.4.2 4 x temperature cycling 1010 c c.3.3.3 x mechanical shock or constant acceleration 2002 2001 b, y1 direction 3,000 g, y1 direction 10(0) 22(0) (see notes 1 & 2) x interim electrical c.3.3.4.3 x burn-in 1015 240 hours minimum at +125c x post burn-in electrical c.3.3.4.3 x steady state life 1005 x final electrical c.3.3.4.3 5 x wire bond evaluation 2011 10(0) wires or 20(1) wires c.3.3.3 c.3.3.5 6 x sem 2018 see method 2018 & note 2 c.3.3.6 notes: 1. subgroups 3, 4, & 5 shall be performed on a samp le of 10 die if the wafer lot is from a qpl/qml lin e. if the die are from commercial wafer lots, then the sample size shall b e 22 die. die from qpl/qml wafers not meeting the q pl/qml requirements and downgraded to commercial grade sha ll not be used. 2. subgroups 3, 4 & 5 shall be performed in the ord er listed in table 1. subgroup 6 may be performed a t any time.
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 19 semiconductor enhanced element evaluation subgroup class test mil-std-750 quantity mil-prf- 38534 reference k method condition (accept number) paragraph 1 x element electrical a. may perform at wafer level b. all failures shall be removed from the lot perform at room ambient 100% c.3.3.1 2 x element visual 2069, 2070, 2072, 2073 100% c.3.3.2 3 x internal visual 2069, 2070, 2072, 2073, 2074 10(0) or 22(0) (notes 1 & 2) c.3.3.3 c.3.3.4.2 4 x temperature cycling 1051 c c.3.3.3 x surge current (when applicable) 4066 a or b as specified x constant acceleration 2006 2001 y1 direction 20,000 g / 10,000 g for pd 10w 10(0) 22(0) (see notes 1 & 2) x interim electrical c.3.3.4.3 x high temperature reverse bias (htrb) 1039 1042 1038 a b a x interim electrical & delta complete within 16 hrs of htrb completion x burn-in 240 hours 1039, 1042 1038 1040 b a b x post burn-in electrical c.3.3.4.3 x steady state life 1000 hours 1026 1037 1042 1048 x final electrical c.3.3.4.3 5 x wire bond evaluation 2011 10(0) wires or 20(1) wires c.3.3.3 c.3.3.5 6 x sem 2018 2077 see method 2018 or 2077 & note 2 c.3.3.6 notes: 1. subgroups 3, 4, & 5 shall be performed on a samp le of 10 die if the wafer lot is from a qpl/qml lin e. if the die are from commercial wafer lots, then the sample size shall b e 22 die. die from qpl/qml wafers not meeting the q pl/qml requirements and downgraded to commercial grade sha ll not be used. 2. subgroups 3, 4 & 5 shall be performed in the ord er listed in table 1. subgroup 6 may be performed a t any time.
size code ident no. unspecified tolerances dwg no. rev. sheet a 00136 n/a DOC200103 c 20 passive components enhanced element evaluation part type test requirements paragraph sample size allowable rejects ceramic capacitors (production lot definition shall be per m55681 or m 123 for chips, or m49470 t-level for stacks) m55681 frl s or m123 (chips) n/a n/a n/a n/a dscc dwg cots (chips) ultrasonic scan or csam m123 100% n/a group a m123 m123 m123 group b, subgroups 1 & 2 m123 m123 m123 t-level m49470 (stacked) n/a n/a n/a n/a general purpose m49470, ultrasonic scan or csam m4 9470 for t-level 100% n/a dscc dwg or cots group a m49470 for t-level m49470 for t-level m49470 for t-level (stacked) group b, subgroups 2, 4 & 5b m49470 for t-level m49470 for t-level m49470 for t- level tantalum chip capacitors (note: stacking tantalum chips will require a repea t of the entire group a in m55365 with minimum weibull c and surge current option c. produ ction lot definition shall be per m55365.) m55365 group a (weibull c minimum with surge current option c) m55365 m55365 m55365 dscc dwg, cots group a (weibull c minimum with surge current option c) m55365 m55365 m55365 group b m55365 m55365 m55365 resistor chips (note: gluing one resistor chip on top of another to change a design or save on real estate is not al lowable without extensive design/process verification, long term testing, and hybrid re-qualification. product ion lot definition shall be per m55342). m55342 frl r or s n/a n/a n/a n/a dscc dwg, cots group a m55342 for t-level m55342 fo r t-level m55342 for t-level group b m55342 for t-level m55342 for t-level m553 42 for t-level magnetics (transformers, inductors, coils) (note: stacking m agnetics will require a repeat of the thermal cycli ng plus electrical measurements as specified in group a of mil-std-981 . design, workmanship and materials/processes shall conform to mil- std-981 requirements. custom group a mil-std-981 mil-std-981 mil-std-981 group b mil-std-981 mil-std-981 mil-std-981

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